1. Field of the Invention
The present invention relates to a high withstand voltage semiconductor device and a method for manufacturing the same, and particularly to a high withstand voltage semiconductor device in which a state in which current conducts and a state in which current is cut off are implemented by voltage of a control electrode.
2. Description of the Background Art
Hereinafter, with reference to FIGS. 40-55, the structure and operation of a conventional high withstand voltage semiconductor device will be described. FIG. 40 is a partial cross sectional view of a first example of the conventional high withstand voltage semiconductor device.
Referring to FIG. 40, an n.sup.- layer 2 is formed on a main surface of a p-type semiconductor substrate 1. An n.sup.+ buried diffusion region 8 is formed at a boundary portion of n.sup.- layer 2 and p-type semiconductor substrate 1. Furthermore, a p diffusion region 7 is formed such that it penetrates n.sup.- layer 2 in the direction of the depth to reach a main surface of p-type semiconductor substrate 1. A p-channel MOS transistor 14 is formed at a surface of n.sup.- layer 2. P-channel MOS transistor 14 consists of a p.sup.- diffusion region 5, a p.sup.+ diffusion region 3 and a gate electrode (control electrode) 9.
An n.sup.+ diffusion region 4 is formed adjacent to p.sup.+ diffusion region 3. Furthermore, an n diffusion region 4a is formed such that it surrounds p.sup.+ diffusion region 3 and n.sup.+ diffusion region 4. A source electrode 11 is formed such that it contacts both n.sup.+ diffusion region 4 and p.sup.+ diffusion region 3. Source electrode 11 extends on gate electrode 9 and p.sup.- diffusion region 5 with an oxide film 10 interposed. A p.sup.+ diffusion region 6 is formed contiguous to one end of p.sup.- diffusion region 5. A drain electrode 12 is formed on p.sup.+ diffusion region 6 surface. Furthermore, a substrate electrode (back-surface electrode) 13 is formed on a back surface of p-type semiconductor substrate 1.
Referring now to FIGS. 41-43, operation of the high withstand voltage semiconductor device shown in FIG. 40 will be described. Referring firstly to FIGS. 41 and 42, off-operation of the device will be described. FIGS. 41 and 42 show in steps a state of a depletion layer in the high withstand voltage semiconductor device shown in FIG. 40 at the time of off-operation.
Referring firstly to FIGS. 41 and 42, electric potentials of drain electrode 12 and substrate electrode 13 are adapted to be 0V and a positive electric potential (+Vcc) is applied to gate electrode 9 and source electrode 11. This causes a depletion layer to widen mainly from a pn junction B which is an interface of n.sup.- layer 2 and p-type semiconductor substrate 1, a pn junction A which is an interface of n.sup.- layer 2 and p diffusion region 7, and a pn junction C which is an interface of n.sup.- layer 2 and p.sup.- diffusion region 5.
At this point, a depletion layer extending from pn junction A normally widens more easily due to the influence of a depletion layer extending from pn junction B. Accordingly, the electric field in the vicinity of pn junction A is maintained to a relatively small value. This effect is realized by optimizing concentration of p-type semiconductor substrate 1, n-type impurity concentration contained in n.sup.- layer 2 and the thickness of n.sup.- layer 2, and is generally referred to as RESURF (REduced SURface Field) effect.
On the other hand, a portion of the depletion layer extending from pn junction C widens towards n.sup.- layer 2 and at the same time makes p.sup.- diffusion region 5 depleted, since p.sup.- diffusion region 5 is a low concentration region. Gate electrode 9 and source electrode 11 formed overlapped above p.sup.- diffusion region 5 form a two-stage field plate. This promotes depletion of p.sup.- diffusion region 5 and relaxes an electric field of pn junction C in the vicinity of gate electrode 9.
If the conditions of each element are optimized, a higher positive electric potential can be applied. Eventually, the withstand voltage is determined by junction of n.sup.+ buried diffusion region 8 and p-type semiconductor substrate 1. At that time, n.sup.- layer 2 and p.sup.- diffusion region 5 have almost been depleted. Thus, the off-state can be maintained.
Referring now to FIG. 43, the on-operation will be described. FIG. 43 shows an on-state of the conventional high withstand voltage semiconductor device shown in FIG. 40. Referring to FIG. 43, a potential of gate electrode 9 is lowered relative to that of source electrode 11. This inverts that surface of n.sup.- layer 2 directly under gate electrode 9 to p-type. This allows a hole current to flow from p.sup.+ diffusion region 3 to p.sup.+ diffusion region 6 via p.sup.- diffusion region 5 as shown by the arrows in FIG. 43. This implements the on-state. Most of the resistance of the device in the on-state comes from a resistance value of p.sup.- diffusion region 5. Therefore, it is effective to lower the resistance of p.sup.- diffusion region 5 in order to reduce the resistance of the device in the on-state. However, in order to ensure a high withstand voltage, p.sup.- diffusion region 5 is required to be nearly depleted in the off-state. Accordingly, there is an upper limit (optimal value) existing naturally in p-type impurity concentration contained in p.sup.- diffusion region 5.
Referring now to FIGS. 44-47, a second example of the conventional high withstand voltage semiconductor device will be described. FIG. 44 is a partial cross sectional view of the second example of the conventional high withstand voltage semiconductor device. Referring to FIG. 44, it differs from the first example of the high withstand voltage semiconductor device shown in FIG. 40 in that an n.sup.+ type diffusion 15 is formed within p.sup.+ diffusion region 6. Other than that structure, the device is the same as the high withstand voltage semiconductor device shown in FIG. 40.
Referring now to FIGS. 45-47, operation of the high withstand voltage semiconductor device shown in FIG. 44 will be described. FIGS. 45 and 46 show in steps a state of depletion layer in the high withstand voltage semiconductor device shown in FIG. 44 at the time of off-operation. The description of the off-operation will not be repeated here since it is the same as the description in the case of the first example of the high withstand voltage semiconductor device shown in FIG. 40.
Referring now to FIG. 47, on-operation of the second example of the high withstand voltage semiconductor device will be described. FIG. 47 shows an on-state of the second example of the high withstand voltage semiconductor device.
Referring to FIG. 47, an electric potential of gate electrode 9 is decreased relative to that of source electrode 11. This allows the surface of n.sup.- layer 2 directly under gate electrode 9 to be inverted to p-type. This allows a hole current 37b to flow from p.sup.+ diffusion region 3 to p.sup.+ diffusion region 6 via p.sup.- diffusion region 5. Responsively, an electron current 37a from n.sup.+ diffusion region 15 into both p.sup.- diffusion region 5 and n.sup.- layer 2. This implements a state in which many electrons and holes are stored and causes conductivity modulation. As a result, the on-state will be implemented. In other words, the second example of the high withstand voltage semiconductor device described above serves to operate as a p-channel IGBT.
FIG. 48 is a bird's eye view of the entire structure of the second example of the high withstand voltage semiconductor device described above.
Referring now to FIGS. 49-52, a third example of the conventional high withstand voltage semiconductor device will described. FIG. 49 is a partial cross sectional view of the third example of the high withstand voltage semiconductor device.
Referring to FIG. 49, a buried oxide film 17 is formed on a surface of a semiconductor substrate 16. N.sup.- layer 2 is formed on buried oxide film 17. Furthermore, a trench 22 is formed at a predetermined position at n.sup.- layer 2. An oxide film 18 is formed on an inner surface of trench 22. A polysilicon layer 19 is buried inside oxide film 18. Other than that structure, the high withstand voltage semiconductor device is similar to the first example of the high withstand voltage semiconductor device shown in FIG. 40.
Referring now to FIGS. 50-52, operation of the third example of the high withstand voltage semiconductor device will be described. FIGS. 50 and 51 show in steps a state of a depletion layer in the high withstand voltage semiconductor device at the time of off-operation. Referring to these figures, similar to the first example of the high withstand voltage semiconductor device described above, electric potentials of drain electrode 12 and substrate electrode 13 are set to be 0V and a positive electric potential (+V) is applied to gate electrode 9 and source electrode 11. This allows a depletion layer to extend mainly from a pn junction which is an interface of p.sup.- diffusion region 5 and n.sup.- layer 2 and from a pn junction which is an interface of p.sup.+ diffusion region 6 and n.sup.- layer 2.
At that time, the depletion layer starts to extend simultaneously from an interface of n.sup.- layer 2 and buried oxide film 17. This contributes to relaxation of electric field. As a result, the RESURF effect described above is obtained. The RESURF effect is described, for example, in S. Merchant et al. "Realization of High Breakdown Voltage (&gt;700V) in Thin SOI Devices" Proc. of 3rd ISPSD, pp.31-35, 1991. Although on-operation of the third example of the high withstand voltage semiconductor device is shown in FIG. 52, its on-operation is not described here since it is the same as the on-operation of the first example of the high withstand voltage semiconductor device described above.
Referring now to FIGS. 53-55, a fourth example of the conventional high withstand voltage semiconductor device will be described. FIG. 53 is a partial sectional view of the fourth example of the conventional high withstand voltage semiconductor device.
Referring to FIG. 53, in the fourth example of the high withstand voltage semiconductor device, p.sup.+ diffusion region 3 and a p diffusion region 3a are formed in n.sup.- layer 2, and n.sup.+ diffusion region 4 is formed at a surface of p.sup.+ diffusion region 3. Furthermore, an n.sup.+ diffusion region 15a is formed such that it is spaced apart from p.sup.+ diffusion region 3. Furthermore, gate electrode 9 is formed on p diffusion region 3a positioned between n.sup.+ diffusion region 4 and n.sup.- layer 2 with oxide film 10 interposed. Furthermore, source electrode 11 is formed in contact with surfaces of both p.sup.+ diffusion region 3 and n.sup.+ diffusion region 4. Drain electrode 12 is formed in contact with a surface of n.sup.+ diffusion region 15a.
Referring now to FIGS. 54 and 55, operation of the fourth example of the high withstand voltage semiconductor device will be described. FIG. 54 shows a state of a depletion layer of the fourth example of the high withstand voltage semiconductor device at the time of off-operation.
Referring to FIG. 54, electric potentials of source electrode 11, gate electrode 9 and substrate electrode 13 are adapted to be 0V, and a positive electric potential is applied to drain electrode 12. This allows a depletion layer to extend mainly from pn junction A which is an interface of p diffusion region 3a and n.sup.- layer 2. At the same time, the depletion layer extends from an interface B of n.sup.- layer 2 and buried oxide film 17. This promotes expansion of the depletion layer, thus further widening the depletion layer. In other words, the RESURF effect is obtained. Consequently, a high withstand voltage device is obtained.
The on-operation will now be described. FIG. 55 shows an on-state of the fourth example of the high withstand voltage semiconductor device. Referring to FIG. 55, electric potentials of source electrode 11 and substrate electrode 13 are adapted to be 0V, an electric potential of gate electrode 9 is increased relative to that of source electrode 11, and a positive electric potential (+Vcc) is applied to drain electrode 12. This allows a surface of p.sup.+ diffusion region 3 directly under gate electrode 9 to be inverted to n-type, thereby forming an inverted region 38. This allows electrons from n.sup.+ diffusion region 4 to reach n.sup.- layer 2 and n.sup.+ diffusion region 15a via inverted region 38. Consequently, the on-operation will be implemented.
In the first to third examples of the conventional high withstand voltage semiconductor device described above, the resistance value of p.sup.- diffusion region 5 is the factor which almost determines the resistance value of the high withstand voltage semiconductor device at the time of on-operation. Therefore, it is desired that the resistance of p.sup.- diffusion region 5 be decreased. For that purpose, the use of a technique which increases p-type impurity concentration contained in p.sup.- diffusion region 5 is generally considered. However, this restrains the widening of the depletion layer within p.sup.- diffusion region 5. Consequently, the electric field tends to be higher within the depletion layer and the withstand voltage of the high withstand voltage semiconductor device will be undesirably decreased.
Furthermore, in the fourth example of the conventional high withstand voltage semiconductor device described above, the resistance value of n.sup.- layer 2 serves as the factor which determines the resistance value of the high withstand voltage semiconductor device at the time of on-operation. Therefore, it is desired that the resistance of n.sup.- layer 2 be decreased. As a technique for achieving that, similar to the case mentioned above, the use of a technique which increases n-type impurity concentration contained in n.sup.- layer 2 is considered. However, in this case also, similar to the first to third examples described above, the widening of the depletion layer within n.sup.- layer 2 is restrained and the withstand voltage of the high withstand voltage semiconductor device will be degraded.
Thus, with the conventional high withstand voltage semiconductor device, it has been difficult to realize both decreased resistance value of the device at the time of on-operation and increased withstand voltage of the device at the time of off-operation.